gossamer 0.0.1
a very lightweight app framework for SAMD and SAML chips
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dma_util.h
1#pragma once
2
3#include "sam.h"
4
6#ifndef _SAMD51_
7
8typedef enum {
9 DMA_CONFIG_LOOP = 1 << 0,
10 DMA_CONFIG_RUNSTDBY = 1 << 1,
11} dma_configuration_flags_t;
12
13typedef enum {
14 DMA_INCREMENT_NONE = 0,
15 DMA_INCREMENT_SOURCE = (1 << 0),
16 DMA_INCREMENT_DESTINATION = (1 << 1),
17 DMA_INCREMENT_BOTH = (1 << 1) | (1 << 0),
18} dma_address_increment_t;
19
20
21typedef enum {
22 DMA_TRIGGER_ACTION_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
23 DMA_TRIGGER_ACTION_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
24 DMA_TRIGGER_ACTION_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
25} dma_trigger_action_t;
26
27typedef enum {
28 // First item here is for any transfer errors. A transfer error is
29 // flagged if a bus error is detected during an AHB access or when
30 // the DMAC fetches an invalid descriptor
31 DMA_CALLBACK_TRANSFER_ERROR,
32 DMA_CALLBACK_TRANSFER_DONE,
33 DMA_CALLBACK_CHANNEL_SUSPEND,
34 DMA_CALLBACK_N, // Number of available callbacks
35} dma_callback_type_t;
36
37typedef enum {
38 DMA_BEAT_SIZE_BYTE = 0, // 8-bit
39 DMA_BEAT_SIZE_HWORD, // 16-bit
40 DMA_BEAT_SIZE_WORD, // 32-bit
41} dma_beat_size_t;
42
43typedef enum {
44 DMA_EVENT_OUTPUT_DISABLE = 0, // Disable event generation
45 DMA_EVENT_OUTPUT_BLOCK, // Event strobe when block xfer complete
46 DMA_EVENT_OUTPUT_RESERVED,
47 DMA_EVENT_OUTPUT_BEAT, // Event strobe when beat xfer complete
48} dma_event_output_selection_t;
49
50typedef enum {
51 DMA_BLOCK_ACTION_NONE = 0,
52 // Channel in normal operation and sets transfer complete interrupt
53 // flag after block transfer
54 DMA_BLOCK_ACTION_INTERRUPT,
55 // Trigger channel suspend after block transfer and sets channel
56 // suspend interrupt flag once the channel is suspended
57 DMA_BLOCK_ACTION_SUSPEND,
58 // Sets transfer complete interrupt flag after a block transfer and
59 // trigger channel suspend. The channel suspend interrupt flag will
60 // be set once the channel is suspended.
61 DMA_BLOCK_ACTION_INTERRUPT_AND_SUSPEND,
62} dma_block_action_t;
63
64// DMA step selection. This bit determines whether the step size setting
65// is applied to source or destination address.
66typedef enum {
67 DMA_STEPSEL_DESTINATION = 0,
68 DMA_STEPSEL_SOURCE,
69} dma_stepsel_t;
70
71// Address increment step size. These bits select the address increment step
72// size. The setting apply to source or destination address, depending on
73// STEPSEL setting.
74typedef enum {
75 DMA_STEPSIZE_1 = 0, // beat size * 1
76 DMA_STEPSIZE_2, // beat size * 2
77 DMA_STEPSIZE_4, // beat size * 4
78 DMA_STEPSIZE_8, // etc...
79 DMA_STEPSIZE_16,
80 DMA_STEPSIZE_32,
81 DMA_STEPSIZE_64,
82 DMA_STEPSIZE_128,
83} dma_stepsize_t;
84
85// higher numbers are higher priority
86typedef enum {
87 DMA_PRIORITY_0, // lowest (default)
88 DMA_PRIORITY_1,
89 DMA_PRIORITY_2,
90 DMA_PRIORITY_3, // highest
91} dma_priority_t;
92
93
94typedef enum {
95 DMA_STATUS_OK = 0,
96 DMA_STATUS_ERR_NOT_FOUND,
97 DMA_STATUS_ERR_NOT_INITIALIZED,
98 DMA_STATUS_ERR_INVALID_ARG,
99 DMA_STATUS_ERR_IO,
100 DMA_STATUS_ERR_TIMEOUT,
101 DMA_STATUS_BUSY,
102 DMA_STATUS_SUSPEND,
103 DMA_STATUS_ABORTED,
104 DMA_STATUS_JOBSTATUS = -1 // For printStatus() function
105} dma_status_t;
106
107#endif