gossamer 0.0.0
a very lightweight app framework for SAMD and SAML chips
Loading...
Searching...
No Matches
dma_util.h
1#ifndef DMA_UTIL_H_INCLUDED
2#define DMA_UTIL_H_INCLUDED
3
4#include "sam.h"
5
7#ifndef _SAMD51_
8
9typedef enum {
10 DMA_CONFIG_LOOP = 1 << 0,
11 DMA_CONFIG_RUNSTDBY = 1 << 1,
12} dma_configuration_flags_t;
13
14typedef enum {
15 DMA_INCREMENT_NONE = 0,
16 DMA_INCREMENT_SOURCE = (1 << 0),
17 DMA_INCREMENT_DESTINATION = (1 << 1),
18 DMA_INCREMENT_BOTH = (1 << 1) | (1 << 0),
19} dma_address_increment_t;
20
21
22typedef enum {
23 DMA_TRIGGER_ACTION_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
24 DMA_TRIGGER_ACTION_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
25 DMA_TRIGGER_ACTION_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
26} dma_trigger_action_t;
27
28typedef enum {
29 // First item here is for any transfer errors. A transfer error is
30 // flagged if a bus error is detected during an AHB access or when
31 // the DMAC fetches an invalid descriptor
32 DMA_CALLBACK_TRANSFER_ERROR,
33 DMA_CALLBACK_TRANSFER_DONE,
34 DMA_CALLBACK_CHANNEL_SUSPEND,
35 DMA_CALLBACK_N, // Number of available callbacks
36} dma_callback_type_t;
37
38typedef enum {
39 DMA_BEAT_SIZE_BYTE = 0, // 8-bit
40 DMA_BEAT_SIZE_HWORD, // 16-bit
41 DMA_BEAT_SIZE_WORD, // 32-bit
42} dma_beat_size_t;
43
44typedef enum {
45 DMA_EVENT_OUTPUT_DISABLE = 0, // Disable event generation
46 DMA_EVENT_OUTPUT_BLOCK, // Event strobe when block xfer complete
47 DMA_EVENT_OUTPUT_RESERVED,
48 DMA_EVENT_OUTPUT_BEAT, // Event strobe when beat xfer complete
49} dma_event_output_selection_t;
50
51typedef enum {
52 DMA_BLOCK_ACTION_NONE = 0,
53 // Channel in normal operation and sets transfer complete interrupt
54 // flag after block transfer
55 DMA_BLOCK_ACTION_INTERRUPT,
56 // Trigger channel suspend after block transfer and sets channel
57 // suspend interrupt flag once the channel is suspended
58 DMA_BLOCK_ACTION_SUSPEND,
59 // Sets transfer complete interrupt flag after a block transfer and
60 // trigger channel suspend. The channel suspend interrupt flag will
61 // be set once the channel is suspended.
62 DMA_BLOCK_ACTION_INTERRUPT_AND_SUSPEND,
63} dma_block_action_t;
64
65// DMA step selection. This bit determines whether the step size setting
66// is applied to source or destination address.
67typedef enum {
68 DMA_STEPSEL_DESTINATION = 0,
69 DMA_STEPSEL_SOURCE,
70} dma_stepsel_t;
71
72// Address increment step size. These bits select the address increment step
73// size. The setting apply to source or destination address, depending on
74// STEPSEL setting.
75typedef enum {
76 DMA_STEPSIZE_1 = 0, // beat size * 1
77 DMA_STEPSIZE_2, // beat size * 2
78 DMA_STEPSIZE_4, // beat size * 4
79 DMA_STEPSIZE_8, // etc...
80 DMA_STEPSIZE_16,
81 DMA_STEPSIZE_32,
82 DMA_STEPSIZE_64,
83 DMA_STEPSIZE_128,
84} dma_stepsize_t;
85
86// higher numbers are higher priority
87typedef enum {
88 DMA_PRIORITY_0, // lowest (default)
89 DMA_PRIORITY_1,
90 DMA_PRIORITY_2,
91 DMA_PRIORITY_3, // highest
92} dma_priority_t;
93
94
95typedef enum {
96 DMA_STATUS_OK = 0,
97 DMA_STATUS_ERR_NOT_FOUND,
98 DMA_STATUS_ERR_NOT_INITIALIZED,
99 DMA_STATUS_ERR_INVALID_ARG,
100 DMA_STATUS_ERR_IO,
101 DMA_STATUS_ERR_TIMEOUT,
102 DMA_STATUS_BUSY,
103 DMA_STATUS_SUSPEND,
104 DMA_STATUS_ABORTED,
105 DMA_STATUS_JOBSTATUS = -1 // For printStatus() function
106} dma_status_t;
107
108#endif
109
110#endif // DMA_UTIL_H_INCLUDED