1#ifndef DMA_UTIL_H_INCLUDED
2#define DMA_UTIL_H_INCLUDED
10 DMA_CONFIG_LOOP = 1 << 0,
11 DMA_CONFIG_RUNSTDBY = 1 << 1,
12} dma_configuration_flags_t;
15 DMA_INCREMENT_NONE = 0,
16 DMA_INCREMENT_SOURCE = (1 << 0),
17 DMA_INCREMENT_DESTINATION = (1 << 1),
18 DMA_INCREMENT_BOTH = (1 << 1) | (1 << 0),
19} dma_address_increment_t;
23 DMA_TRIGGER_ACTION_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
24 DMA_TRIGGER_ACTION_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
25 DMA_TRIGGER_ACTION_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
26} dma_trigger_action_t;
32 DMA_CALLBACK_TRANSFER_ERROR,
33 DMA_CALLBACK_TRANSFER_DONE,
34 DMA_CALLBACK_CHANNEL_SUSPEND,
39 DMA_BEAT_SIZE_BYTE = 0,
45 DMA_EVENT_OUTPUT_DISABLE = 0,
46 DMA_EVENT_OUTPUT_BLOCK,
47 DMA_EVENT_OUTPUT_RESERVED,
48 DMA_EVENT_OUTPUT_BEAT,
49} dma_event_output_selection_t;
52 DMA_BLOCK_ACTION_NONE = 0,
55 DMA_BLOCK_ACTION_INTERRUPT,
58 DMA_BLOCK_ACTION_SUSPEND,
62 DMA_BLOCK_ACTION_INTERRUPT_AND_SUSPEND,
68 DMA_STEPSEL_DESTINATION = 0,
97 DMA_STATUS_ERR_NOT_FOUND,
98 DMA_STATUS_ERR_NOT_INITIALIZED,
99 DMA_STATUS_ERR_INVALID_ARG,
101 DMA_STATUS_ERR_TIMEOUT,
105 DMA_STATUS_JOBSTATUS = -1